mttc wrote:

> I not sure that this effect on clock. the OS determine the Time by
> counting the tick interrupt, even it come late.

I agree that the mechanism seems improbable to you, but
what other mechanisms are there ? The beauty of SMI,
is the computer is defenseless against it. If the SMI
runs longer than a clock tick, the clock tick is lost
and not counted. To lose time consistently, and with
more error than can be accounted for by the quartz
timing elements, requires a violation of the expectations
of the OS designer. The clock tick interrupt is assigned
a high priority, to help prevent this sort of thing.

Run the DPC check. While DPC has nothing to do with the
clock tick interrupt, a high DPC latency is also an
indication that something is preventing the system from
being responsive. In some cases, a BIOS update has fixed
a DPC issue.

Paul